EP20K100CF144C7ES vs EP20K100CF144C7 Comparaison
Comparaison détaillée côte à côte de EP20K100CF144C7ES par Intel et EP20K100CF144C7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K100CF144C7ES | EP20K100CF144C7 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $171,00 | $28,40 |
| Family | APEX-20K | APEX-20K Field Programmable Gate Array |
| Typical Gates | 100,000 | — |
| Logic Elements | 4,160 | — |
| Embedded Memory (RAM bits) | 53,248 | — |
| User I/O Pins | 93 | — |
| DLLs / Clock Management | 4 DLLs | — |
| Boîtier | 144-LQFP (20x20 mm) | — |
| Type de montage | Surface Mount | Surface Mount |
| Speed Grade | C7 (commercial, mid-speed) | C7 (commercial) |
| Température de fonctionnement | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Core Voltage | 1.8 V (typical APEX-20K VCCINT) | — |
| I/O Voltage Reference | MultiVolt I/O - 3.3 V / 5 V tolerant | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming File Format | Quartus II / MAX+PLUS II SOF / POF | — |
| Variant Suffix | ES (engineering sample / special order) | — |
| Niveau MSL | [DATA_NEEDED: MSL Level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20K |
| Logic Elements / Cells | — | 4,160 |
| Total RAM Bits | — | 53,248 |
| Number of Logic Elements | — | 4,160 |
| Number of I/O | — | 93 |
| Number of Gates | — | 100,000 system gates |
| Voltage - Supply | — | 1.8 V core, 3.3 V I/O (typical APEX-20K rails) |
| Boîtier / Format | — | 144-LQFP |
| Package Dimensions | — | 22 x 22 mm, 0.5 mm pitch |
| Process Technology | — | 0.18 micron CMOS SRAM |
| Configuration Mode | — | Passive Serial, JTAG (IEEE 1149.1) |
| PLLs | — | 4 (per APEX-20K family architecture) |