EP20K100EBC356-3N vs EP20K100EFC144-1 Vergleich

Detaillierter Direktvergleich von EP20K100EBC356-3N von Altera und EP20K100EFC144-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K100EBC356-3N EP20K100EFC144-1
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $92,00 $61,75
Series APEX-20KE —
Family APEX 20K —
Logic Elements / Cells 4160 —
System Gates 100,000 —
Embedded Memory (bits) 53,248 —
Embedded System Blocks (ESBs) 26 Yes (memory + dedicated logic)
Maximum User I/Os 246 —
Anzahl der Pins 356 —
Gehäuse 356-LBGA (Ball Grid Array) —
Package Dimensions 45 x 45 mm —
Ball Pitch 1.27 mm —
Process Technology 0.22 µm CMOS 0.15-µm all-layer copper
Core Supply Voltage 1.8 V —
Propagation Delay 1.6 ns (speed grade -3N) 1.6 ns
Maximum Internal Frequency 250 MHz —
Betriebstemperatur 0 °C to +85 °C 0 °C to 85 °C (commercial)
Montageart Surface Mount Surface Mount
Programmable Interface JTAG (IEEE 1149.1) —
I/O Standards Supported LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ —
RoHS-Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance]
Device Family — APEX 20KE
Device Type — FPGA (Field Programmable Gate Array)
Typical Gates — 100,000
Maximum System Gates — 263,000
Logic Elements — 4,160
User I/Os — 93
PLLs — 4
Package Type — 144-ball FBGA (13x13 mm, 1.0 mm pitch)
Core Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Voltage Support — 1.8 V / 2.5 V / 3.3 V (multiVolt I/O)
Configuration Method — SRAM (volatile) - external boot PROM required
Boundary-Scan Support — IEEE 1149.1 (JTAG)

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern