EP20K100EBC356-3N vs EP20K100EFC144-1 对比

详细并排对比 EP20K100EBC356-3N 出自 Altera 和 EP20K100EFC144-1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K100EBC356-3N EP20K100EFC144-1
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $92.00 $61.75
Series APEX-20KE —
Family APEX 20K —
Logic Elements / Cells 4160 —
System Gates 100,000 —
Embedded Memory (bits) 53,248 —
Embedded System Blocks (ESBs) 26 Yes (memory + dedicated logic)
Maximum User I/Os 246 —
引脚数 356 —
封装 356-LBGA (Ball Grid Array) —
Package Dimensions 45 x 45 mm —
Ball Pitch 1.27 mm —
Process Technology 0.22 µm CMOS 0.15-µm all-layer copper
Core Supply Voltage 1.8 V —
Propagation Delay 1.6 ns (speed grade -3N) 1.6 ns
Maximum Internal Frequency 250 MHz —
工作温度 0 °C to +85 °C 0 °C to 85 °C (commercial)
安装类型 Surface Mount Surface Mount
Programmable Interface JTAG (IEEE 1149.1) —
I/O Standards Supported LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ —
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance]
Device Family — APEX 20KE
Device Type — FPGA (Field Programmable Gate Array)
Typical Gates — 100,000
Maximum System Gates — 263,000
Logic Elements — 4,160
User I/Os — 93
PLLs — 4
Package Type — 144-ball FBGA (13x13 mm, 1.0 mm pitch)
Core Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Voltage Support — 1.8 V / 2.5 V / 3.3 V (multiVolt I/O)
Configuration Method — SRAM (volatile) - external boot PROM required
Boundary-Scan Support — IEEE 1149.1 (JTAG)

数据手册与资源

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