EP20K100EBC652-2X vs EP20K100EBC356-3N Vergleich
Detaillierter Direktvergleich von EP20K100EBC652-2X von Altera und EP20K100EBC356-3N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100EBC652-2X | EP20K100EBC356-3N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $85,00 | $92,00 |
| Family | APEX 20KE | APEX 20K |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | 26 |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | — |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Gehäuse | 652-ball BGA (EBC652) | 356-LBGA (Ball Grid Array) |
| Speed Grade | -2 (faster commercial) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | 0.22 µm CMOS |
| Betriebstemperatur | 0C to +85C (commercial) | 0 °C to +85 °C |
| Montageart | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | — |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Series | — | APEX-20KE |
| Logic Elements / Cells | — | 4160 |
| System Gates | — | 100,000 |
| Embedded Memory (bits) | — | 53,248 |
| Maximum User I/Os | — | 246 |
| Anzahl der Pins | — | 356 |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |
| Core Supply Voltage | — | 1.8 V |
| Propagation Delay | — | 1.6 ns (speed grade -3N) |
| Maximum Internal Frequency | — | 250 MHz |
| Programmable Interface | — | JTAG (IEEE 1149.1) |
| I/O Standards Supported | — | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ |