EP20K100FC144-1 vs EP20K100EFC144-1 Vergleich
Detaillierter Direktvergleich von EP20K100FC144-1 von Altera und EP20K100EFC144-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100FC144-1 | EP20K100EFC144-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $78,50 | $61,75 |
| Series | APEX-20K | — |
| Family | APEX-20K | — |
| Typical Gates | 100,000 | 100,000 |
| Logic Elements | 4,160 | 4,160 |
| Embedded RAM Bits | 53,248 | — |
| User I/O Pins | 93 | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Number of Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Number of Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Core Voltage | 2.5 V | — |
| I/O Voltage | 3.3 V (PCI-compatible) | — |
| Speed Grade | -1 (slowest) | — |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | 0 °C to 85 °C (commercial) |
| Gehäuse | 144-LQFP | — |
| Montageart | Surface Mount | Surface Mount |
| Programmable Interface | JTAG / IEEE 1532 (ISP) | — |
| PCI Compliance | 3.3V PCI compliant | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | APEX 20KE |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Maximum System Gates | — | 263,000 |
| Embedded System Blocks (ESBs) | — | Yes (memory + dedicated logic) |
| User I/Os | — | 93 |
| Propagation Delay | — | 1.6 ns |
| PLLs | — | 4 |
| Package Type | — | 144-ball FBGA (13x13 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V (multiVolt I/O) |
| Process Technology | — | 0.15-µm all-layer copper |
| Configuration Method | — | SRAM (volatile) - external boot PROM required |
| Boundary-Scan Support | — | IEEE 1149.1 (JTAG) |