EP20K100FC324-1V vs EP20K100EFC324-1N Vergleich
Detaillierter Direktvergleich von EP20K100FC324-1V von Intel und EP20K100EFC324-1N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100FC324-1V | EP20K100EFC324-1N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $118,40 | $108,00 |
| Series | APEX-20K® | — |
| Number of Logic Elements / Cells | 4160 | — |
| Total RAM Bits | 53248 | — |
| Number of Gates (typical) | 100000 | — |
| Number of I/O | 252 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Supply Voltage - Core (VCCINT) | 2.375 V to 2.625 V | — |
| Supply Voltage - I/O (VCCIO) | 3.0 V / 3.3 V / 5.0 V tolerant (per I/O standard) | — |
| Speed Grade | -1V (commercial) | — |
| Betriebstemperatur | 0C to +85C (commercial) | 0 C to 85 C |
| Montageart | Surface Mount | — |
| Gehäuse / Bauform | 324-FBGA (FineLine BGA, 19x19 mm) | — |
| Supplier Device Package | 324-FBGA | — |
| Number of PLLs | 4 | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL, GTL+, HSTL | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Programming Interface | JTAG (IEEE 1149.1) / in-system | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | APEX-20KE |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | — | 4160 |
| Typical Gates | — | 100,000 |
| Maximum User I/O | — | 246 |
| Embedded System Blocks (ESBs) | — | 53248 bits |
| Gehäuse | — | 324-BGA (FineLine BGA) |
| Propagation Delay | — | 1.6 ns |
| Internal Operating Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| I/O Standard Support | — | LVDS, SSTL, HSTL, LVTTL, LVCMOS |
| Process Technology | — | 0.15 µm all-layer copper CMOS |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming Technology | — | SRAM-based (volatile, requires configuration device) |
| MultiVolt I/O | — | 1.8 V core with 3.3 V / 5.0 V I/O support |