EP20K100FC324-3 vs EP20K100EFC324-1N Vergleich
Detaillierter Direktvergleich von EP20K100FC324-3 von Intel und EP20K100EFC324-1N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100FC324-3 | EP20K100EFC324-1N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $42,10 | $108,00 |
| Series | APEX 20K | — |
| Family | APEX 20K (non-KE) | APEX-20KE |
| System Gates | 100,000 | — |
| Logic Elements | 4,160 | — |
| Maximum Logic Blocks | 26 | — |
| Embedded Memory (RAM bits) | 53,248 | — |
| User I/O Pins | 252 | — |
| Total RAM bits | 53,248 | — |
| Process Technology | 0.22 µm CMOS | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 167 MHz | — |
| Propagation Delay | 1.6 ns | 1.6 ns |
| Speed Grade | -3 (slowest) | — |
| Gehäuse | 324-pin FBGA (Fine-pitch BGA) | 324-BGA (FineLine BGA) |
| Package Body Size | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Betriebstemperatur | 0 °C to 85 °C (Commercial) | 0 C to 85 C |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Montageart | Surface Mount | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | — | 4160 |
| Typical Gates | — | 100,000 |
| Maximum User I/O | — | 246 |
| Embedded System Blocks (ESBs) | — | 53248 bits |
| Internal Operating Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| I/O Standard Support | — | LVDS, SSTL, HSTL, LVTTL, LVCMOS |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming Technology | — | SRAM-based (volatile, requires configuration device) |
| MultiVolt I/O | — | 1.8 V core with 3.3 V / 5.0 V I/O support |