EP20K100FC324-3 vs EP20K100EFC324-1N 对比

详细并排对比 EP20K100FC324-3 出自 Intel 和 EP20K100EFC324-1N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K100FC324-3 EP20K100EFC324-1N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $42.10 $108.00
Series APEX 20K —
Family APEX 20K (non-KE) APEX-20KE
System Gates 100,000 —
Logic Elements 4,160 —
Maximum Logic Blocks 26 —
Embedded Memory (RAM bits) 53,248 —
User I/O Pins 252 —
Total RAM bits 53,248 —
Process Technology 0.22 µm CMOS 0.15 µm all-layer copper CMOS
Core Supply Voltage 2.5 V —
Maximum Internal Frequency 167 MHz —
Propagation Delay 1.6 ns 1.6 ns
Speed Grade -3 (slowest) —
封装 324-pin FBGA (Fine-pitch BGA) 324-BGA (FineLine BGA)
Package Body Size 45 x 45 mm —
Ball Pitch 1.27 mm —
工作温度 0 °C to 85 °C (Commercial) 0 C to 85 C
Programming Interface IEEE 1149.1 JTAG —
安装类型 Surface Mount —
RoHS 状态 [DATA_NEEDED: RoHS status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Device Type — FPGA (Field Programmable Gate Array)
Logic Elements (LEs) — 4160
Typical Gates — 100,000
Maximum User I/O — 246
Embedded System Blocks (ESBs) — 53248 bits
Internal Operating Frequency — 250 MHz
Core Voltage — 1.8 V
I/O Standard Support — LVDS, SSTL, HSTL, LVTTL, LVCMOS
JTAG Support — IEEE 1149.1 boundary-scan
Programming Technology — SRAM-based (volatile, requires configuration device)
MultiVolt I/O — 1.8 V core with 3.3 V / 5.0 V I/O support

数据手册与资源

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