EP20K200CB356C7N vs EP20K200BC356-1 Vergleich

Detaillierter Direktvergleich von EP20K200CB356C7N von Intel und EP20K200BC356-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP20K200BC356-1 EP20K200BC356-1 - APEX-20K 200K-Gate FPGA | Altera

EP20K200BC356-1 - APEX-20K 200K-Gate FPGA | Altera

EP20K200BC356-1 Obsolete

Spezifikationsvergleich

Parameter EP20K200CB356C7N EP20K200BC356-1
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $92,00 $335,00
Family APEX 20KC —
Series EP20K200 —
System Gates 200,000 —
Logic Elements / Cells 8,320 8320
Maximum Operating Frequency 3571.6 MHz (internal equivalent) —
Propagation Delay 1.48 ns —
User I/Os 263 —
Input Terminals 267 —
Supply Voltage (Nominal) 1.8 V —
Process Technology 0.15 um CMOS 0.22 um
Betriebstemperatur 0C to +85C (Commercial) —
Gehäuse 356-ball PBGA (S-PBGA) —
Montageart Surface Mount Surface Mount
Embedded Memory ESBs (dual-port RAM/ROM/FIFO) —
Clock Management PLL with up to 4 outputs —
JTAG Support Yes (IEEE 1149.1) —
In-System Programmable Yes —
RoHS-Status unknown [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1]
Product Function — APEX-20K Field Programmable Gate Array (FPGA)
Logic Family — CMOS
Equivalent System Gates — 200K gates
Total RAM Bits — 106496 bits
Maximale Taktfrequenz — 250 MHz
Core Supply Voltage — 2.5 V
User I/O Count — 277
Anzahl der Pins — 356
Gehäuse / Bauform — 356-LBGA
Package Code — LBGA
Package Shape — Square
Propagation Delay (tPD) — 2.5 ns (from -1N variant listing)
Betriebstemperaturbereich — 0 to 85 C (commercial, per -1N variant listing)
Lead-Free Finish — [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free]

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