EP20K200CB356C7N vs EP20K200BC356-1 对比
详细并排对比 EP20K200CB356C7N 出自 Intel 和 EP20K200BC356-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP20K200CB356C7N - APEX 20KC FPGA 200K Gates 356-BGA | Intel / Altera
EP20K200CB356C7N Obsolete
规格对比
| 参数 | EP20K200CB356C7N | EP20K200BC356-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $92.00 | $335.00 |
| Family | APEX 20KC | — |
| Series | EP20K200 | — |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | 8320 |
| Maximum Operating Frequency | 3571.6 MHz (internal equivalent) | — |
| Propagation Delay | 1.48 ns | — |
| User I/Os | 263 | — |
| Input Terminals | 267 | — |
| Supply Voltage (Nominal) | 1.8 V | — |
| Process Technology | 0.15 um CMOS | 0.22 um |
| 工作温度 | 0C to +85C (Commercial) | — |
| 封装 | 356-ball PBGA (S-PBGA) | — |
| 安装类型 | Surface Mount | Surface Mount |
| Embedded Memory | ESBs (dual-port RAM/ROM/FIFO) | — |
| Clock Management | PLL with up to 4 outputs | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| In-System Programmable | Yes | — |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] |
| Product Function | — | APEX-20K Field Programmable Gate Array (FPGA) |
| Logic Family | — | CMOS |
| Equivalent System Gates | — | 200K gates |
| Total RAM Bits | — | 106496 bits |
| 最大时钟频率 | — | 250 MHz |
| Core Supply Voltage | — | 2.5 V |
| User I/O Count | — | 277 |
| 引脚数 | — | 356 |
| 封装 / 外壳 | — | 356-LBGA |
| Package Code | — | LBGA |
| Package Shape | — | Square |
| Propagation Delay (tPD) | — | 2.5 ns (from -1N variant listing) |
| 工作温度范围 | — | 0 to 85 C (commercial, per -1N variant listing) |
| Lead-Free Finish | — | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] |