EP20K200CF484C9N vs EP20K200CF484I9 Vergleich

Detaillierter Direktvergleich von EP20K200CF484C9N von Altera und EP20K200CF484I9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K200CF484C9N EP20K200CF484I9
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $201,04 $138,00
Family APEX 20KC APEX 20KC (APEX 20K with ESB/CAM)
Device Type FPGA (Field-Programmable Gate Array) —
Typical Gates 200,000 200,000
Logic Elements 8,320 —
Embedded System Block (ESB) Bits 106,496 —
Maximum User I/O 376 376
Maximale Taktfrequenz 250 MHz —
Process Technology 0.15 um CMOS 0.15 um CMOS
Core Supply Voltage (VCCINT) 1.8 V 1.8 V nominal (1.71 V to 1.89 V)
I/O Supply Voltage (VCCIO) 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) —
Gehäuse 484-pin FineLine BGA (FBGA) 484-ball FineLine BGA (FBGA), 1.00 mm pitch
Speed Grade C9 (250 MHz) -9 (lowest speed in EP20K200 family)
Temperature Grade Industrial (0C to +85C) —
Montageart Surface Mount (BGA) —
Configuration Scheme SRAM-based, supports passive serial/parallel and JTAG —
MSL-Level 3 (per JEDEC J-STD-020) —
RoHS-Status Compliant unknown - confirm with supplier (legacy part)
Series — APEX 20KC
Logic Elements (Cells) — 8,320
Dedicated Inputs — 4
Total Terminals — 484 (balls)
Operating Temperature Grade — Industrial (I)
Junction Temperature Range — -40 C to +100 C
Configuration Method — SRAM, JTAG in-system programmable
Lifecycle — Obsolete - EOL announced by Altera/Intel in 2008

Datenblätter & Ressourcen

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