EP20K200CF484I9 vs EP20K200CF484C9N Vergleich
Detaillierter Direktvergleich von EP20K200CF484I9 von Altera und EP20K200CF484C9N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K200CF484I9 | EP20K200CF484C9N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $138,00 | $201,04 |
| Series | APEX 20KC | — |
| Family | APEX 20KC (APEX 20K with ESB/CAM) | APEX 20KC |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Typical Gates | 200,000 | 200,000 |
| Logic Elements (Cells) | 8,320 | — |
| Maximum User I/O | 376 | 376 |
| Dedicated Inputs | 4 | — |
| Total Terminals | 484 (balls) | — |
| Gehäuse | 484-ball FineLine BGA (FBGA), 1.00 mm pitch | 484-pin FineLine BGA (FBGA) |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | 1.8 V |
| Operating Temperature Grade | Industrial (I) | — |
| Junction Temperature Range | -40 C to +100 C | — |
| Speed Grade | -9 (lowest speed in EP20K200 family) | C9 (250 MHz) |
| Configuration Method | SRAM, JTAG in-system programmable | — |
| RoHS-Status | unknown - confirm with supplier (legacy part) | Compliant |
| Lifecycle | Obsolete - EOL announced by Altera/Intel in 2008 | — |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Maximale Taktfrequenz | — | 250 MHz |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Temperature Grade | — | Industrial (0C to +85C) |
| Montageart | — | Surface Mount (BGA) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |