EP20K200CF484I9 vs EP20K200CF484C9N Comparación
Comparación detallada lado a lado de EP20K200CF484I9 por Altera y EP20K200CF484C9N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K200CF484I9 | EP20K200CF484C9N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $138,00 | $201,04 |
| Series | APEX 20KC | — |
| Family | APEX 20KC (APEX 20K with ESB/CAM) | APEX 20KC |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Typical Gates | 200,000 | 200,000 |
| Logic Elements (Cells) | 8,320 | — |
| Maximum User I/O | 376 | 376 |
| Dedicated Inputs | 4 | — |
| Total Terminals | 484 (balls) | — |
| Encapsulado | 484-ball FineLine BGA (FBGA), 1.00 mm pitch | 484-pin FineLine BGA (FBGA) |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | 1.8 V |
| Operating Temperature Grade | Industrial (I) | — |
| Junction Temperature Range | -40 C to +100 C | — |
| Speed Grade | -9 (lowest speed in EP20K200 family) | C9 (250 MHz) |
| Configuration Method | SRAM, JTAG in-system programmable | — |
| Estado RoHS | unknown - confirm with supplier (legacy part) | Compliant |
| Lifecycle | Obsolete - EOL announced by Altera/Intel in 2008 | — |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Frecuencia de reloj máxima | — | 250 MHz |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Temperature Grade | — | Industrial (0C to +85C) |
| Tipo de montaje | — | Surface Mount (BGA) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |