EP20K30EQC208-1 vs EP20K30EQC208-2 Vergleich

Detaillierter Direktvergleich von EP20K30EQC208-1 von Altera und EP20K30EQC208-2 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K30EQC208-1 EP20K30EQC208-2
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $34,90 $7,92
Series APEX-20KE —
Family FPGA APEX 20K Family APEX 20KE
Number of Logic Elements/Cells 1200 —
Number of Gates 30000 (30K gates) —
Number of Macro Cells [DATA_NEEDED: Number of macro cells] —
Total RAM Bits 24576 —
Number of User I/O 125 —
Voltage - Supply 1.71 V to 1.89 V —
Core Voltage 1.8 V —
Technology 0.22 um —
Gehäuse / Bauform 208-BFQFP —
Supplier Device Package 208-PQFP (28x28) —
Package Code FQFP —
Terminal Form Gull wing —
Number of Terminals 208 —
Terminal Pitch 0.50 mm —
Package Shape Square —
Montageart Surface Mount Surface Mount (PQFP with gull-wing leads)
Speed Grade -1 -2 (2.69 ns pin-to-pin)
Betriebstemperaturbereich [DATA_NEEDED: operating temperature range] —
RoHS-Status unknown [DATA_NEEDED: RoHS compliance status]
Device Logic — FPGA (SRAM-based)
Typical Gates — 30,000
Logic Elements — 1,200
Embedded Memory (RAM bits) — 24,576
Maximum User I/O — 125
Dedicated Inputs — 4
Gehäuse — 208-BFQFP (PQFP-208)
Core Supply Voltage — 1.71 V to 1.89 V
I/O Standard — LVDS-compatible, 1.8 V / 2.5 V / 3.3 V (per bank)
Maximale Taktfrequenz — 160 MHz
Propagation Delay — 2.69 ns
Configuration Interface — IEEE 1149.1 JTAG, Passive serial, Active serial
Betriebstemperatur — [DATA_NEEDED: operating temperature range]
Process Technology — 1.8 V CMOS, MultiCore architecture
MSL-Level — [DATA_NEEDED: MSL rating]

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern