EP20K30EQC208-1 vs EP20K30EQC208-2 对比

详细并排对比 EP20K30EQC208-1 出自 Altera 和 EP20K30EQC208-2 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K30EQC208-1 EP20K30EQC208-2
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $34.90 $7.92
Series APEX-20KE —
Family FPGA APEX 20K Family APEX 20KE
Number of Logic Elements/Cells 1200 —
Number of Gates 30000 (30K gates) —
Number of Macro Cells [DATA_NEEDED: Number of macro cells] —
Total RAM Bits 24576 —
Number of User I/O 125 —
Voltage - Supply 1.71 V to 1.89 V —
Core Voltage 1.8 V —
Technology 0.22 um —
封装 / 外壳 208-BFQFP —
Supplier Device Package 208-PQFP (28x28) —
Package Code FQFP —
Terminal Form Gull wing —
Number of Terminals 208 —
Terminal Pitch 0.50 mm —
Package Shape Square —
安装类型 Surface Mount Surface Mount (PQFP with gull-wing leads)
Speed Grade -1 -2 (2.69 ns pin-to-pin)
工作温度范围 [DATA_NEEDED: operating temperature range] —
RoHS 状态 unknown [DATA_NEEDED: RoHS compliance status]
Device Logic — FPGA (SRAM-based)
Typical Gates — 30,000
Logic Elements — 1,200
Embedded Memory (RAM bits) — 24,576
Maximum User I/O — 125
Dedicated Inputs — 4
封装 — 208-BFQFP (PQFP-208)
Core Supply Voltage — 1.71 V to 1.89 V
I/O Standard — LVDS-compatible, 1.8 V / 2.5 V / 3.3 V (per bank)
最大时钟频率 — 160 MHz
Propagation Delay — 2.69 ns
Configuration Interface — IEEE 1149.1 JTAG, Passive serial, Active serial
工作温度 — [DATA_NEEDED: operating temperature range]
Process Technology — 1.8 V CMOS, MultiCore architecture
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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