EP20K400BI652-2V vs EP20K400CB652C9ES Vergleich
Detaillierter Direktvergleich von EP20K400BI652-2V von Intel und EP20K400CB652C9ES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400BI652-2V - 400K Gates APEX 20K FPGA 652-BGA | Intel / Altera
EP20K400BI652-2V Obsolete
Spezifikationsvergleich
| Parameter | EP20K400BI652-2V | EP20K400CB652C9ES |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $84,50 | $195,00 |
| Family | APEX 20K | APEX 20KC |
| Series | APEX 20K (EPLD-based SOPC) | APEX 20KC |
| System Gates | 400,000 | — |
| Logic Elements | 16,640 | — |
| Maximum User I/O | 502 | — |
| Embedded Memory (bits) | 212,992 | — |
| Embedded Memory Blocks | ESBs (Embedded System Blocks) | — |
| Macros (per Mouser listing) | 1664 | — |
| Logic Family | CMOS | — |
| Process Technology | 0.22 μm | 0.15 µm CMOS |
| Core Supply Voltage (VCCINT) | 2.5 V | — |
| Propagation Delay | 2.5 ns (typical) | — |
| Internal Performance | 200 MHz (speed grade -2) | — |
| Betriebstemperatur | 0 °C to +85 °C (industrial, "I") | — |
| Gehäuse | 652-ball FineLine BGA (35 × 35 mm, 1.27 mm pitch) | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Configuration Interface | JTAG (IEEE 1149.1) / Passive Serial | — |
| Logic Elements / Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Embedded Memory (Bits) | — | 212992 |
| Number of User I/O | — | 488 |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Number of Logic Array Blocks | — | 1040 |
| Maximum Operating Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| Betriebstemperaturbereich | — | 0°C to +85°C (Commercial) |
| Gehäuse / Bauform | — | 652-BGA |
| MSL-Level | — | 3 (168 Hours) |
| Packaging | — | Tray |
| Programmability Type | — | In-system programmable (SRAM-based) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL |
| JTAG (IEEE 1149.1) | — | Yes |
| PLL | — | Yes (4-phase) |