EP20K400BI652-2V vs EP20K400CB652C9ES Comparison

Detailed side-by-side comparison of EP20K400BI652-2V by Intel and EP20K400CB652C9ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400BI652-2V EP20K400CB652C9ES
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family APEX 20K APEX 20KC
Series APEX 20K (EPLD-based SOPC) APEX 20KC
System Gates 400,000 —
Logic Elements 16,640 —
Maximum User I/O 502 —
Embedded Memory (bits) 212,992 —
Embedded Memory Blocks ESBs (Embedded System Blocks) —
Macros (per Mouser listing) 1664 —
Logic Family CMOS —
Process Technology 0.22 μm 0.15 µm CMOS
Core Supply Voltage (VCCINT) 2.5 V —
Propagation Delay 2.5 ns (typical) —
Internal Performance 200 MHz (speed grade -2) —
Operating Temperature 0 °C to +85 °C (industrial, "I") —
Package 652-ball FineLine BGA (35 × 35 mm, 1.27 mm pitch) —
Mounting Type Surface Mount (BGA) Surface Mount
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Configuration Interface JTAG (IEEE 1149.1) / Passive Serial —
Logic Elements / Cells — 16640
Total System Gates — 400000
Embedded Memory (Bits) — 212992
Number of User I/O — 488
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Number of Logic Array Blocks — 1040
Maximum Operating Frequency — 250 MHz
Core Voltage — 1.8 V
Operating Temperature Range — 0°C to +85°C (Commercial)
Package / Case — 652-BGA
MSL Level — 3 (168 Hours)
Packaging — Tray
Programmability Type — In-system programmable (SRAM-based)
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL
JTAG (IEEE 1149.1) — Yes
PLL — Yes (4-phase)

Datasheets & Resources

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