EP20K400CF672C7GA vs EP20K400CF672C-8 Vergleich
Detaillierter Direktvergleich von EP20K400CF672C7GA von Intel und EP20K400CF672C-8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400CF672C7GA | EP20K400CF672C-8 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,50 | $95,00 |
| Series | APEX-20KC | — |
| Logic Elements | 212992 | 16,640 |
| Number of LABs/CLBs | 488 | — |
| Total RAM Bits | 16640 | — |
| Number of I/O | [DATA_NEEDED: max user I/O count] | — |
| Number of Gates | 400000 | — |
| Voltage - Supply | 2.5 V core | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Gehäuse / Bauform | 672-BBGA (FineLine BGA) | — |
| Betriebstemperatur | 0C to +85C | — |
| Speed Grade | C7 (7 ns pin-to-pin) | -8 |
| Process Technology | 0.18 um CMOS | 0.15 µm all-layer copper CMOS |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Family | — | APEX 20K |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Maximum User I/O | — | 488 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |