EP20K400CF672C7GA vs EP20K400CF672C-8 Comparaison
Comparaison détaillée côte à côte de EP20K400CF672C7GA par Intel et EP20K400CF672C-8 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400CF672C7GA | EP20K400CF672C-8 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,50 | $95,00 |
| Series | APEX-20KC | — |
| Logic Elements | 212992 | 16,640 |
| Number of LABs/CLBs | 488 | — |
| Total RAM Bits | 16640 | — |
| Number of I/O | [DATA_NEEDED: max user I/O count] | — |
| Number of Gates | 400000 | — |
| Voltage - Supply | 2.5 V core | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Boîtier / Format | 672-BBGA (FineLine BGA) | — |
| Température de fonctionnement | 0C to +85C | — |
| Speed Grade | C7 (7 ns pin-to-pin) | -8 |
| Process Technology | 0.18 um CMOS | 0.15 µm all-layer copper CMOS |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Family | — | APEX 20K |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Maximum User I/O | — | 488 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |