EP20K400FC672-3V vs EP20K400FI672-3V Vergleich
Detaillierter Direktvergleich von EP20K400FC672-3V von Altera und EP20K400FI672-3V von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400FC672-3V | EP20K400FI672-3V |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $152,00 | $285,00 |
| Family | APEX 20KC | APEX 20K (EP20K400) |
| Series | APEX-20KC | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements / Cells | 16640 | — |
| System Gates | 400000 | — |
| Total RAM Bits | 212992 | — |
| Number of I/O | 502 | — |
| Number of LABs/CLBs | 1664 | — |
| Number of Logic Elements | 16640 | — |
| Supply Voltage (Core) | 1.71 V to 1.89 V | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (industrial) |
| Gehäuse / Bauform | 672-BBGA, FCBGA | — |
| Supplier Device Package | 672-FBGA (27x27) | — |
| Process Technology | 0.22 µm | 0.18 µm CMOS, 4 metal layers |
| Maximum Internal Frequency | 167 MHz (typical) | — |
| Pin-to-Pin Delay | 3.6 ns | — |
| Speed Grade | -3 | -3 (faster) |
| Programmability Type | In-system (JTAG IEEE 1149.1) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 400,000 |
| Typical Gates | — | [DATA_NEEDED: typical gates value] |
| Embedded Memory (bits) | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Total User I/O + Dedicated Inputs | — | 496 + 6 (variant dependent) |
| Maximale Taktfrequenz | — | 714.2 MHz |
| Core Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Gehäuse | — | 672-ball FineLine BGA (BBGA), 1.0 mm pitch |
| Programmable via JTAG | — | Yes (IEEE 1149.1) |
| Supported I/O Standards | — | LVCMOS, LVTTL, SSTL, GTL+, HSTL |
| Configuration Modes | — | JTAG, passive serial, passive parallel |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |