EP20K400FI672-2 vs EP20K400FC672-3 Vergleich
Detaillierter Direktvergleich von EP20K400FI672-2 von Altera und EP20K400FC672-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteSpezifikationsvergleich
| Parameter | EP20K400FI672-2 | EP20K400FC672-3 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,40 | $138,00 |
| Family | APEX-20K | APEX 20K |
| Logic Elements | 16640 | — |
| Maximum Gates | 400,000 gates | — |
| User I/Os | 502 | — |
| Embedded Memory Bits | 212992 | — |
| Number of Macros | 1664 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Maximum Internal Frequency | 200 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Betriebstemperatur | 0 °C to +85 °C (Commercial) | 0 °C to 85 °C |
| Package Type | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) | — |
| PLLs (Phase-Locked Loops) | 4 | — |
| Configuration Modes | JTAG, Passive Serial, Passive Parallel | — |
| RoHS-Status | Lead-free / RoHS Compliant | [DATA_NEEDED: RoHS status] |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Device Logic Elements | — | 16,640 cells |
| Typical Gate Count | — | 400,000 system gates |
| Maximum User I/Os | — | 502 |
| Internal Performance | — | 167 MHz |
| Logic Family | — | CMOS, SRAM-based |
| Gehäuse | — | 672-pin FC-FBGA |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Speed Grade | — | -3 (commercial fastest) |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| Lebenszyklusstatus | — | Obsolete / Legacy |