EP20K400FI672-2 vs EP20K400FC672-3 对比
详细并排对比 EP20K400FI672-2 出自 Altera 和 EP20K400FC672-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 Obsolete规格对比
| 参数 | EP20K400FI672-2 | EP20K400FC672-3 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $92.40 | $138.00 |
| Family | APEX-20K | APEX 20K |
| Logic Elements | 16640 | — |
| Maximum Gates | 400,000 gates | — |
| User I/Os | 502 | — |
| Embedded Memory Bits | 212992 | — |
| Number of Macros | 1664 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Maximum Internal Frequency | 200 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| 工作温度 | 0 °C to +85 °C (Commercial) | 0 °C to 85 °C |
| Package Type | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) | — |
| PLLs (Phase-Locked Loops) | 4 | — |
| Configuration Modes | JTAG, Passive Serial, Passive Parallel | — |
| RoHS 状态 | Lead-free / RoHS Compliant | [DATA_NEEDED: RoHS status] |
| 安装类型 | Surface Mount (BGA) | Surface Mount |
| Device Logic Elements | — | 16,640 cells |
| Typical Gate Count | — | 400,000 system gates |
| Maximum User I/Os | — | 502 |
| Internal Performance | — | 167 MHz |
| Logic Family | — | CMOS, SRAM-based |
| 封装 | — | 672-pin FC-FBGA |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Speed Grade | — | -3 (commercial fastest) |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| 生命周期状态 | — | Obsolete / Legacy |