EP20K400FI672-2N vs EP20K400FC672-3 Vergleich

Detaillierter Direktvergleich von EP20K400FI672-2N von Altera und EP20K400FC672-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K400FI672-2N EP20K400FC672-3
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $188,75 $138,00
Family APEX 20K APEX 20K
Typical Gates 400,000 —
Logic Elements / Cells 16,640 —
Maximum User I/O 488 —
Embedded Memory Bits 212,992 bits —
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count per family datasheet] —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Voltage 2.5 V —
Maximum Frequency 200 MHz —
Gehäuse 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) 672-pin FC-FBGA
Package Body Size 27 x 27 mm —
Terminal Pitch 1.0 mm —
Propagation Delay 3.1 ns 2.5 ns
Speed Grade -2 -3 (commercial fastest)
Betriebstemperatur Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] 0 °C to 85 °C
Feuchtigkeitsempfindlichkeitsgrad (MSL) 3 —
Peak Reflow Temperature 220 °C —
Montageart Surface Mount Surface Mount
RoHS-Status Compliant (lead-free) [DATA_NEEDED: RoHS status]
Configuration Modes PS, PPS, PPA, JTAG —
Supported I/O Standards LVTTL, LVCMOS, SSTL, HSTL —
Device Logic Elements — 16,640 cells
Typical Gate Count — 400,000 system gates
Maximum User I/Os — 502
Internal Performance — 167 MHz
Core Supply Voltage — 2.5 V
Logic Family — CMOS, SRAM-based
Package Code — BGA
Number of Terminals — 672
Terminal Form — Ball (BGA)
Architecture — MultiCore (LUT + Embedded System Blocks)
Programming Method — SRAM, JTAG (ByteBlaster)
Lebenszyklusstatus — Obsolete / Legacy

Datenblätter & Ressourcen

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