EP20K400FI672-2N vs EP20K400FC672-3 对比

详细并排对比 EP20K400FI672-2N 出自 Altera 和 EP20K400FC672-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FI672-2N EP20K400FC672-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $188.75 $138.00
Family APEX 20K APEX 20K
Typical Gates 400,000 —
Logic Elements / Cells 16,640 —
Maximum User I/O 488 —
Embedded Memory Bits 212,992 bits —
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count per family datasheet] —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Voltage 2.5 V —
Maximum Frequency 200 MHz —
封装 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) 672-pin FC-FBGA
Package Body Size 27 x 27 mm —
Terminal Pitch 1.0 mm —
Propagation Delay 3.1 ns 2.5 ns
Speed Grade -2 -3 (commercial fastest)
工作温度 Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] 0 °C to 85 °C
湿敏等级(MSL) 3 —
Peak Reflow Temperature 220 °C —
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant (lead-free) [DATA_NEEDED: RoHS status]
Configuration Modes PS, PPS, PPA, JTAG —
Supported I/O Standards LVTTL, LVCMOS, SSTL, HSTL —
Device Logic Elements — 16,640 cells
Typical Gate Count — 400,000 system gates
Maximum User I/Os — 502
Internal Performance — 167 MHz
Core Supply Voltage — 2.5 V
Logic Family — CMOS, SRAM-based
Package Code — BGA
Number of Terminals — 672
Terminal Form — Ball (BGA)
Architecture — MultiCore (LUT + Embedded System Blocks)
Programming Method — SRAM, JTAG (ByteBlaster)
生命周期状态 — Obsolete / Legacy

数据手册与资源

浏览全部产品 创建 BOM 获取报价