EP20K400FI672-3 vs EP20K400FI672-3N Vergleich
Detaillierter Direktvergleich von EP20K400FI672-3 von Altera und EP20K400FI672-3N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400FI672-3 | EP20K400FI672-3N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Unknown |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $195,00 | $0,00 |
| Family | APEX 20K | — |
| Series | EP20K400 | EP20K400 |
| Logic Elements | 16640 | — |
| Total Gates | up to 400000 | — |
| Embedded RAM | 212992 bits | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Propagation Delay | 3.6 ns | 3.6 ns |
| Maximale Taktfrequenz | 833 MHz | 833 MHz |
| Supply Voltage (Nominal) | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | 2.375 V to 2.625 V |
| Process Technology | CMOS | CMOS |
| Package Type | PBGA (Plastic BGA) | — |
| Package Code | S-PBGA-B672 | — |
| Terminal Count | 672 | 672 terminals |
| Terminal Pitch | 1.000 mm | 1.000 mm |
| Package Shape | Square BGA | — |
| Montageart | Surface Mount | Surface mount |
| Configuration Interface | JTAG (IEEE 1149.1) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| MSL-Level | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| Device Type | — | CMOS loadable programmable logic device |
| Product Family | — | APEX 20K |
| User I/O Count | — | 502 |
| Nominal Supply Voltage | — | 2.5 V |
| Gehäuse | — | S-PBGA-B672 |
| Logic Capacity | — | [DATA_NEEDED: logic capacity] |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| I/O Standard Support | — | [DATA_NEEDED: supported I/O standards] |
| RoHS-Status | — | unknown |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |