EP20K400GC655-1 vs EP20K400GC652-1XV Vergleich
Detaillierter Direktvergleich von EP20K400GC655-1 von Intel und EP20K400GC652-1XV von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete
Spezifikationsvergleich
| Parameter | EP20K400GC655-1 | EP20K400GC652-1XV |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $135,00 | $190,00 |
| Family | APEX 20K | APEX 20K |
| Series | EP20K400 | — |
| Logic Elements | 16,640 | — |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Gehäuse | 655-pin CPGA (Ceramic Pin Grid Array) | — |
| Pin-Anzahl | 655 | — |
| Montageart | Through-Hole | Surface Mount |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0 C to +85 C |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| RoHS-Status | Non-compliant (contains lead in ceramic package) | Compliant (lead-free, V suffix) |
| Logic Elements (Macros) | — | 1664 |
| Typical System Gates | — | 400,000 |
| Embedded SRAM | — | 212,992 bits |
| Logic Family | — | CMOS |
| Package Type | — | BGA-652 (thermally enhanced) |
| Speed Grade | — | -1 (standard) |
| Architecture | — | MultiCore (LUT + EAB + FastTrack interconnect) |
| Programming Interface | — | JTAG (IEEE 1149.1) / passive serial |