EP20K400GC655-1 vs EP20K400GC652-1XV 比較
詳細な並列比較: EP20K400GC655-1 メーカー: Intel および EP20K400GC652-1XV メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete
仕様比較
| パラメータ | EP20K400GC655-1 | EP20K400GC652-1XV |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $135.00 | $190.00 |
| Family | APEX 20K | APEX 20K |
| Series | EP20K400 | — |
| Logic Elements | 16,640 | — |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| パッケージ | 655-pin CPGA (Ceramic Pin Grid Array) | — |
| ピン数 | 655 | — |
| 実装タイプ | Through-Hole | Surface Mount |
| 動作温度 | 0 °C to +85 °C (commercial) | 0 C to +85 C |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| RoHS ステータス | Non-compliant (contains lead in ceramic package) | Compliant (lead-free, V suffix) |
| Logic Elements (Macros) | — | 1664 |
| Typical System Gates | — | 400,000 |
| Embedded SRAM | — | 212,992 bits |
| Logic Family | — | CMOS |
| Package Type | — | BGA-652 (thermally enhanced) |
| Speed Grade | — | -1 (standard) |
| Architecture | — | MultiCore (LUT + EAB + FastTrack interconnect) |
| Programming Interface | — | JTAG (IEEE 1149.1) / passive serial |