EP20K400GC655-1V vs EP20K400GC655-3X Vergleich
Detaillierter Direktvergleich von EP20K400GC655-1V von Altera und EP20K400GC655-3X von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400GC655-1V | EP20K400GC655-3X |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $555,00 | $65,00 |
| Family | APEX 20KE | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Logic Elements | 16,640 | — |
| Typical Gate Count | 400,000 gates | — |
| Embedded Memory | 212,992 bits | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | — |
| Gehäuse | CBGA-655 (Ceramic Ball Grid Array) | — |
| Total Terminals | 655 | — |
| Supply Voltage (Core) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 2.5 ns | — |
| Maximum Internal Frequency | 250 MHz (-1V speed grade) | 167 MHz (speed grade -3) |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| LVDS Support | Yes | — |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 °C | — |
| Qualification | Not Qualified | — |
| Programming Interface | IEEE 1532 / JTAG | — |
| Series | — | APEX-20KC |
| Manufacturer | — | Altera (now Intel FPGA) |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Total RAM Bits | — | 212,992 bits |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| Gehäuse / Bauform | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Montageart | — | Through-Hole (CPGA, ceramic) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Speed Grade | — | -3 (fastest) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |
| RoHS-Status | — | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |