EP20K400GC655-1V vs EP20K400GC655-3X 对比

详细并排对比 EP20K400GC655-1V 出自 Altera 和 EP20K400GC655-3X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400GC655-1V EP20K400GC655-3X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $555.00 $65.00
Family APEX 20KE APEX 20K (MultiCore architecture, LUT + product-term + embedded memory)
Logic Elements 16,640 —
Typical Gate Count 400,000 gates —
Embedded Memory 212,992 bits —
Maximum User I/O 496 —
Dedicated Inputs 6 —
封装 CBGA-655 (Ceramic Ball Grid Array) —
Total Terminals 655 —
Supply Voltage (Core) 2.375 V to 2.625 V (nominal 2.5 V) —
Propagation Delay 2.5 ns —
Maximum Internal Frequency 250 MHz (-1V speed grade) 167 MHz (speed grade -3)
Process Technology 0.22 µm CMOS 0.22 µm CMOS
LVDS Support Yes —
Moisture Sensitivity Level MSL 1 —
Peak Reflow Temperature 220 °C —
Qualification Not Qualified —
Programming Interface IEEE 1532 / JTAG —
Series — APEX-20KC
Manufacturer — Altera (now Intel FPGA)
Logic Elements / Cells — 16,640
System Gates — 400,000
Total RAM Bits — 212,992 bits
Core Supply Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Supply Voltage (VCCIO) — 2.5 V (LVDS support per APEX 20KE datasheet)
封装 / 外壳 — 655-BCPGA (CPGA655, 62.48 x 62.48 mm)
安装类型 — Through-Hole (CPGA, ceramic)
工作温度 — [DATA_NEEDED: operating temperature range]
Speed Grade — -3 (fastest)
Suffix Code — -X (extended / ceramic CPGA variant)
I/O Count — [DATA_NEEDED: max user I/O]
JTAG / Boundary Scan — IEEE 1149.1 (per APEX 20K family)
RoHS 状态 — [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS]

数据手册与资源

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