EP20K400GI655-1X vs EP20K400GI655-1 Vergleich
Detaillierter Direktvergleich von EP20K400GI655-1X von Altera und EP20K400GI655-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoleteSpezifikationsvergleich
| Parameter | EP20K400GI655-1X | EP20K400GI655-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $160,00 | $195,00 |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | — |
| Logic Elements | 16640 | 16640 |
| Number of Terminals | 655 | — |
| User I/O Lines | 502 | — |
| Dedicated Inputs | 4 | 4 |
| Package Type | Ceramic Pin Grid Array (CPGA) | Ceramic Pin Grid Array (CPGA-655) |
| Package Code (JESD-30) | S-CPGA-P655 | — |
| Package Equivalence Code | SPGA655,47X47 | — |
| Package Body Material | CERAMIC (metal-sealed co-fired) | — |
| Speed Grade | -1 | — |
| Propagation Delay | 2.5 ns (typical for -1 grade) | 2.5 ns |
| Process Technology | CMOS, SRAM-based configuration | — |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 1 | — |
| Peak Reflow Temperature | 220 C | 220 C |
| Betriebstemperatur | -40 C to +85 C (industrial) | -40C to +85C (Industrial) |
| Montageart | Through-Hole (PGA) | — |
| RoHS-Status | Compliant | Compliant |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Typical Gates | — | 400000 |
| Maximum User I/O | — | 502 |
| Total Terminals | — | 655 |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Moisture Sensitivity Level | — | MSL 1 |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |