EP20K400GI655-1X vs EP20K400GI655-1 对比
详细并排对比 EP20K400GI655-1X 出自 Altera 和 EP20K400GI655-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X Obsolete规格对比
| 参数 | EP20K400GI655-1X | EP20K400GI655-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $160.00 | $195.00 |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | — |
| Logic Elements | 16640 | 16640 |
| Number of Terminals | 655 | — |
| User I/O Lines | 502 | — |
| Dedicated Inputs | 4 | 4 |
| Package Type | Ceramic Pin Grid Array (CPGA) | Ceramic Pin Grid Array (CPGA-655) |
| Package Code (JESD-30) | S-CPGA-P655 | — |
| Package Equivalence Code | SPGA655,47X47 | — |
| Package Body Material | CERAMIC (metal-sealed co-fired) | — |
| Speed Grade | -1 | — |
| Propagation Delay | 2.5 ns (typical for -1 grade) | 2.5 ns |
| Process Technology | CMOS, SRAM-based configuration | — |
| 湿敏等级（MSL） | 1 | — |
| Peak Reflow Temperature | 220 C | 220 C |
| 工作温度 | -40 C to +85 C (industrial) | -40C to +85C (Industrial) |
| 安装类型 | Through-Hole (PGA) | — |
| RoHS 状态 | Compliant | Compliant |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Typical Gates | — | 400000 |
| Maximum User I/O | — | 502 |
| Total Terminals | — | 655 |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Moisture Sensitivity Level | — | MSL 1 |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |