EP20K600CB652C-8 vs EP20K600CB652C7ES Vergleich

Detaillierter Direktvergleich von EP20K600CB652C-8 von Altera und EP20K600CB652C7ES von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CB652C-8 EP20K600CB652C7ES
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $86,00 $195,00
Series APEX 20KC —
Family APEX 20KC (MultiCore) APEX 20KC
Typical Gates 600,000 —
Logic Elements 24,320 24,320
Embedded RAM 311,296 bits —
User I/Os 488 —
Propagation Delay 1.48 ns (per published source) 1.6 ns
Gehäuse 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch) —
Montageart Surface Mount (thermally enhanced) Surface Mount (BGA)
Betriebstemperatur 0 C to 85 C (commercial) 0 °C to +85 °C (commercial)
Speed Grade -8 (slowest, most timing margin) —
VCCIO Options 1.8 V / 2.5 V / 3.3 V —
Process 0.15 µm all-layer copper metal —
PCI Compliance PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit —
Memory Interface Support DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS —
Configuration Enhanced (EPC) bitstream —
System Gates — 600,000
Maximum System Gates — 1,053,840
Embedded Memory Bits — 311,296
Embedded System Blocks (ESB) — 26
Maximum User I/O — 488
User I/O (this package) — 488 (652-BGA)
Supply Voltage - Core — 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency — 1666.6 MHz
Process Technology — 0.15 µm CMOS
Package Type — 652-ball FineLine BGA
JEDEC Package Code — S-PBGA-B652
Configuration Modes — Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan — IEEE 1149.1 compliant
RoHS-Status — [DATA_NEEDED: RoHS status]
PLLs — 4

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern