EP20K600CB652C-8 vs EP20K600CB652C7ES 对比

详细并排对比 EP20K600CB652C-8 出自 Altera 和 EP20K600CB652C7ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CB652C-8 EP20K600CB652C7ES
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $86.00 $195.00
Series APEX 20KC —
Family APEX 20KC (MultiCore) APEX 20KC
Typical Gates 600,000 —
Logic Elements 24,320 24,320
Embedded RAM 311,296 bits —
User I/Os 488 —
Propagation Delay 1.48 ns (per published source) 1.6 ns
封装 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch) —
安装类型 Surface Mount (thermally enhanced) Surface Mount (BGA)
工作温度 0 C to 85 C (commercial) 0 °C to +85 °C (commercial)
Speed Grade -8 (slowest, most timing margin) —
VCCIO Options 1.8 V / 2.5 V / 3.3 V —
Process 0.15 µm all-layer copper metal —
PCI Compliance PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit —
Memory Interface Support DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS —
Configuration Enhanced (EPC) bitstream —
System Gates — 600,000
Maximum System Gates — 1,053,840
Embedded Memory Bits — 311,296
Embedded System Blocks (ESB) — 26
Maximum User I/O — 488
User I/O (this package) — 488 (652-BGA)
Supply Voltage - Core — 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency — 1666.6 MHz
Process Technology — 0.15 µm CMOS
Package Type — 652-ball FineLine BGA
JEDEC Package Code — S-PBGA-B652
Configuration Modes — Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan — IEEE 1149.1 compliant
RoHS 状态 — [DATA_NEEDED: RoHS status]
PLLs — 4

数据手册与资源

浏览全部产品 创建 BOM 获取报价