EP20K600CB652C7E5 vs EP20K400CB652I7 Vergleich
Detaillierter Direktvergleich von EP20K600CB652C7E5 von Intel und EP20K400CB652I7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K600CB652C7E5 | EP20K400CB652I7 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $175,00 | $149,50 |
| Family | APEX 20KC | APEX 20KC |
| Typical Gate Count | 600K gates | — |
| Logic Elements / Macros | 24,320 | — |
| Maximum User I/O | 488 | — |
| Embedded Memory (EAB bits) | 311,296 bits | — |
| Gehäuse | 652-ball FineLine BGA | BGA-652 (652-ball) |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.15 um CMOS | 0.15 µm CMOS |
| Betriebstemperatur | 0C to +85C (commercial, suffix C7) | — |
| Speed Grade | 7 (-1 speed bin equivalent, E5 suffix) | 7 |
| PLL Count | 4 | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL | — |
| Configuration Scheme | Passive Serial / JTAG / EPC16 / EPC8 | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Non-compliant (JESD-609 e0, contains lead) |
| Lebenszyklusstatus | Obsolete - last time buy has passed | — |
| Device Family | — | Field-Programmable Gate Array (FPGA) |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Maximum Operating Frequency | — | 375.94 MHz |
| Core Supply Voltage | — | 1.8 V |
| I/O Supply Voltage | — | 1.8 V / 3.3 V |
| Package Code (JESD-30) | — | S-PBGA-B652 |
| Terminal Form | — | Ball |
| Package Shape | — | Square |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O] |
| Embedded Memory | — | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM |
| Configuration Method | — | SRAM + JTAG (ISP) |
| Temperature Grade | — | Industrial (-40 °C to +100 °C) |
| Manufacturer Status | — | Obsolete (Intel/Altera legacy FPGA) |