EP20K600CB652C8N vs EP20K600CB652C7ES Vergleich
Detaillierter Direktvergleich von EP20K600CB652C8N von Altera und EP20K600CB652C7ES von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K600CB652C8N | EP20K600CB652C7ES |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $115,00 | $195,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD / FPGA | — |
| System Gates | 600,000 | 600,000 |
| Logic Elements | 24,320 cells | 24,320 |
| Embedded Memory | 311,296 bits | — |
| User I/O Pins | 488 | — |
| Dedicated Inputs | 4 | — |
| Outputs | 480 | — |
| Propagation Delay (typ.) | 1.48 ns | — |
| Pin-to-Pin Timing | 1.78 ns | — |
| Internal Frequency (typ.) | 301.21 MHz | — |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Process Technology | 0.18 µm all-layer copper-metal | 0.15 µm CMOS |
| Speed Grade | C8 | — |
| Betriebstemperatur | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Gehäuse | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Architecture | MultiCore LUT + Embedded System Blocks (ESB) | — |
| Pin-Compatible With | APEX 20KE family | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| Maximum User I/O | — | 488 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Propagation Delay | — | 1.6 ns |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |