EP20K600CB652C8N vs EP20K600CB652C7ES Comparación
Comparación detallada lado a lado de EP20K600CB652C8N por Altera y EP20K600CB652C7ES por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CB652C8N | EP20K600CB652C7ES |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $115,00 | $195,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD / FPGA | — |
| System Gates | 600,000 | 600,000 |
| Logic Elements | 24,320 cells | 24,320 |
| Embedded Memory | 311,296 bits | — |
| User I/O Pins | 488 | — |
| Dedicated Inputs | 4 | — |
| Outputs | 480 | — |
| Propagation Delay (typ.) | 1.48 ns | — |
| Pin-to-Pin Timing | 1.78 ns | — |
| Internal Frequency (typ.) | 301.21 MHz | — |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Process Technology | 0.18 µm all-layer copper-metal | 0.15 µm CMOS |
| Speed Grade | C8 | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Encapsulado | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Architecture | MultiCore LUT + Embedded System Blocks (ESB) | — |
| Pin-Compatible With | APEX 20KE family | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| Maximum User I/O | — | 488 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Propagation Delay | — | 1.6 ns |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |