EP20K600CB652C9N vs EP20K600CB652I9N Vergleich

Detaillierter Direktvergleich von EP20K600CB652C9N von Intel und EP20K600CB652I9N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CB652C9N EP20K600CB652I9N
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $128,00 $158,00
Family APEX 20KC APEX 20KC
Device Type Loadable PLD (FPGA) —
Typical Gates 600,000 —
Logic Elements 24,320 24,320
Maximum User I/O 488 —
Gehäuse BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) 652-BGA (PBGA652)
Process Technology 0.15 micron all-layer copper CMOS 0.15 um CMOS
Core Supply Voltage 1.8 V —
Speed Grade C9 (~1.48 ns propagation delay) —
Architecture MultiCore LUT + embedded system memory (ESB) —
On-chip Memory Embedded system memory blocks (dual-port RAM, FIFO) —
Configuration Interface JTAG (IEEE 1149.1) and serial/PROM configuration —
Betriebstemperatur 0 C to 85 C (commercial) -40C to +100C (Industrial)
Montageart Surface Mount (BGA) —
Pin/Pin Compatibility Pin-compatible with APEX 20KE devices of same package —
Toolchain Altera/Intel Quartus II (legacy APEX support) —
RoHS-Status [DATA_NEEDED: rohs status] —
MSL-Level [DATA_NEEDED: MSL level] —
System Gates — 600,000
Maximum Operating Frequency — 250 MHz
Core Voltage — 1.8 V
I/O Voltage — 3.3 V
Total I/O Pins — 488
General-Purpose I/O — 480
Dedicated Inputs — 4
Terminal Pitch — 1.27 mm
Configuration Method — Passive Serial / Passive Parallel / JTAG
Embedded Memory — ESB (Embedded System Block) RAM / CAM
I/O Standards — LVDS, PCI, LVTTL, LVCMOS

Datenblätter & Ressourcen

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