EP20K600CB652C9N vs EP20K600CB652I9N 对比
详细并排对比 EP20K600CB652C9N 出自 Intel 和 EP20K600CB652I9N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EP20K600CB652I9N - 600K APEX 20KC FPGA, 652-BGA, Industrial | Altera
EP20K600CB652I9N Obsolete规格对比
| 参数 | EP20K600CB652C9N | EP20K600CB652I9N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $128.00 | $158.00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD (FPGA) | — |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O | 488 | — |
| 封装 | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) | 652-BGA (PBGA652) |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.8 V | — |
| Speed Grade | C9 (~1.48 ns propagation delay) | — |
| Architecture | MultiCore LUT + embedded system memory (ESB) | — |
| On-chip Memory | Embedded system memory blocks (dual-port RAM, FIFO) | — |
| Configuration Interface | JTAG (IEEE 1149.1) and serial/PROM configuration | — |
| 工作温度 | 0 C to 85 C (commercial) | -40C to +100C (Industrial) |
| 安装类型 | Surface Mount (BGA) | — |
| Pin/Pin Compatibility | Pin-compatible with APEX 20KE devices of same package | — |
| Toolchain | Altera/Intel Quartus II (legacy APEX support) | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| System Gates | — | 600,000 |
| Maximum Operating Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| I/O Voltage | — | 3.3 V |
| Total I/O Pins | — | 488 |
| General-Purpose I/O | — | 480 |
| Dedicated Inputs | — | 4 |
| Terminal Pitch | — | 1.27 mm |
| Configuration Method | — | Passive Serial / Passive Parallel / JTAG |
| Embedded Memory | — | ESB (Embedded System Block) RAM / CAM |
| I/O Standards | — | LVDS, PCI, LVTTL, LVCMOS |