EP20K600CF1020C9 vs EP20K600CF33C9 Vergleich
Detaillierter Direktvergleich von EP20K600CF1020C9 von Intel und EP20K600CF33C9 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K600CF1020C9 - APEX 20KC FPGA 600K Gates 250MHz 1020-FBGA | Intel
EP20K600CF1020C9 ObsoleteSpezifikationsvergleich
| Parameter | EP20K600CF1020C9 | EP20K600CF33C9 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $165,00 | $171,00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | — |
| System Gates | 600,000 | 600,000 (maximum) |
| Maximum Operating Frequency | 250 MHz | 250 MHz |
| Embedded Memory (ESB) | Configurable dual-port RAM / FIFO / CAM / ROM | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| User I/O Pins | 588 | — |
| Dedicated Inputs | 4 | — |
| Total I/O Count (in/out) | 580 / 580 | — |
| Gehäuse | 1020-ball FC-FBGA (33 x 33 mm, 1.00 mm pitch) | 1020-ball FC-FBGA |
| JESD-30 Package Code | S-PBGA-B1020 | — |
| Betriebstemperatur | 0°C to 85°C (TJ) | — |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (33/66 MHz, 32/64-bit, 3.3 V) | — |
| External Memory Support | DDR SDRAM, ZBT SRAM | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Logic Elements / Cells | — | 24,320 |
| Maximale Taktfrequenz | — | 303.03 MHz |
| Propagation Delay | — | 2.0 ns |
| Core Supply Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | — | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Montageart | — | Surface Mount (BGA) |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | — | Dual-port RAM blocks (per family) |
| Programmability | — | JTAG / IEEE 1149.1 ISP, SRAM-based |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS (per family datasheet) |