EP20K600CF672-3 vs EP20K600CF672-1X Vergleich

Detaillierter Direktvergleich von EP20K600CF672-3 von Intel und EP20K600CF672-1X von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CF672-3 EP20K600CF672-1X
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $99,50 $95,00
Family APEX 20KC —
Typical Gates 600,000 —
Maximum System Gates 2,432,000 —
Maximum Logic Elements 2,432 —
Embedded System Memory 311,040 bits (380 Kbits ESB) —
User I/O Pins 488 —
Gehäuse 672-ball FineLine BGA 672-ball BGA (CF672), 1.27 mm pitch
Speed Grade -3 -1 (industrial speed grade, X = lead-free)
Process Technology 0.18 µm CMOS 0.18 um SRAM CMOS
PLLs 4 4
Maximum Internal Frequency 180 MHz (per APEX 20K family datasheet) —
Configuration Modes PS, PPS, PPA, JTAG, EPC2/EPC16 —
I/O Standards Supported LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI —
Montageart Surface Mount Surface Mount (BGA)
Betriebstemperatur [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial temp range]
RoHS-Status Lead-free / RoHS compliant (per Alibaba listing) Compliant (per Alibaba distributor listing: "RoHS Compliant")
Series — APEX 20KC
Device Family — APEX 20KC MultiCore FPGA
Maximum Typical Gates — 600,000
Logic Elements — 31,104 (per Altera APEX 20KC datasheet family)
Embedded System Blocks (ESBs) — up to 256
Embedded Memory (max bits) — [DATA_NEEDED: ESB RAM bits]
Maximum User I/O — [DATA_NEEDED: max user I/O count]
Configuration Method — SRAM, JTAG (IEEE 1149.1), EPC passive serial
Versorgungsspannung — [DATA_NEEDED: VCCINT/VCCIO]
MSL-Level — [DATA_NEEDED: MSL rating]

Datenblätter & Ressourcen

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