EP20K600CF672C-7 vs EP20K600CF672C6 Vergleich

Detaillierter Direktvergleich von EP20K600CF672C-7 von Altera und EP20K600CF672C6 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CF672C-7 EP20K600CF672C6
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.620,00 $480,00
Device Family APEX 20KC —
Typical Gates 600,000 —
Logic Elements 24,576 —
Maximum User I/O 508 —
Embedded Memory (ESB) 311 kbits —
Number of Terminals 672 —
Package Type 672-BBGA, FCBGA —
Package Dimensions 45 x 45 mm —
Ball Pitch 1.27 mm —
Process Technology 0.18 µm all-layer copper-metal (APEX 20KC) 0.18 µm CMOS, 6 metal layers
Speed Grade -7 -6 (C6)
Propagation Delay 1.48 ns —
Betriebstemperatur 0 °C to 85 °C (Commercial) 0 °C to +85 °C (commercial)
Configuration Interface EPC (Enhanced Configuration) device family —
Montageart Surface Mount —
Lead-Free / RoHS [DATA_NEEDED: lead-free/RoHS status not stated in verified web data] —
Family — APEX 20KC
Typical Gate Count — 600,000 gates
Logic Elements (LEs) — 24,320
Embedded System Blocks (ESBs) — 160 (each 2,048 bits)
Maximum Embedded RAM — 311,296 bits (311 kbit)
Maximum User I/O Pins — 508
Gehäuse — 672-ball FineLine BGA (CF672)
Package Body Size — 27 mm × 27 mm
Core Voltage — 1.8 V
I/O Standards Supported — LVCMOS, LVTTL, HSTL, SSTL, GTL+
Embedded PLLs — 4
Configuration Method — SRAM-based, JTAG, EPC16/EPC2
RoHS-Status — Non-RoHS (legacy process)

Datenblätter & Ressourcen

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