EP20K600CF672I8 vs EP20K600CF672I9 Vergleich

Detaillierter Direktvergleich von EP20K600CF672I8 von Altera und EP20K600CF672I9 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CF672I8 EP20K600CF672I9
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $195,00 $152,00
Family APEX 20KC APEX 20KC
Device Type SPLD / FPGA —
Logic Elements / Cells 24,320 24,320
Macros (Logic Cells) 2432 —
Typical Gate Count 600,000 gates —
Embedded Memory 311,296 bits [DATA_NEEDED: total RAM bits]
User I/Os 488 to 508 —
Anzahl der Pins 652 (functional) / 672 (BGA balls) —
Propagation Delay (typical) 1.48 ns —
Internal Frequency (max) [DATA_NEEDED: max internal frequency in MHz] —
Core Supply Voltage 1.8 V —
Process Technology 0.15 µm all-layer copper 0.15 µm CMOS
Betriebstemperatur 0 °C to +85 °C (Industrial) —
Package Type 672-ball BGA, 45 x 45 mm, 1.27 mm pitch —
Montageart Surface Mount Surface Mount (BGA)
RoHS-Status Compliant per legacy product records [DATA_NEEDED: RoHS status]
Configuration Interface JTAG / Passive Serial —
Design Tool Quartus II (legacy MAX+PLUS II) —
System Gates — 600,000
Maximum Operating Frequency — 250 MHz
Core Voltage — 1.8 V
Gehäuse — 672-pin FC-FBGA
Temperature Grade — Industrial (-40°C to +85°C)
Speed Grade — 9 (fastest bin)
User I/O Pins — 311 (max)
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count]
PLLs — Up to 4
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS
Configuration Mode — Passive Serial / JTAG
Maximum Seated Height — 2.1 mm
MSL-Level — [DATA_NEEDED: MSL level]
Lead-Free — [DATA_NEEDED: lead-free]

Datenblätter & Ressourcen

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