EP2A25F672C7N vs EP2A25F672C7 Vergleich

Detaillierter Direktvergleich von EP2A25F672C7N von Altera und EP2A25F672C7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672C7N EP2A25F672C7
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $195,00 $118,00
Family APEX II —
Logic Elements 24,320 cells 25,000
System Gates Approximately 900,000 —
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.15-um all-layer copper, up to 8 metal layers
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
Betriebstemperatur 0 °C to 85 °C (commercial) 0C to +85C (Commercial)
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM —
PLLs Up to 4 —
Montageart Surface Mount —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Product Family — APEX II
Maximum System Gates — 1,650,000
Maximum RAM Bits — 422,976
User I/O Count — 492
Gehäuse — 672-ball FCBGA (FineLine BGA)
Supply Voltage (Core) — 1.5 V
LVDS Data Rate — 1 Gbps per channel (True-LVDS)
I/O Standards Supported — LVDS, LVPECL, PCML, HyperTransport
Speed Grade — -7
Configuration Mode — Passive Serial, Passive Parallel, JTAG
Embedded System Blocks (ESB) — Yes - RAM, ROM, CAM, multiplier support

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern