EP2A25F672C7N vs EP2A25F672C7 比較
詳細な並列比較: EP2A25F672C7N メーカー: Altera および EP2A25F672C7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2A25F672C7N | EP2A25F672C7 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $195.00 | $118.00 |
| Family | APEX II | — |
| Logic Elements | 24,320 cells | 25,000 |
| System Gates | Approximately 900,000 | — |
| User I/Os | 492 | — |
| Propagation Delay (tPD) | 1.69 ns | — |
| Internal Operating Frequency | Up to 500 MHz | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.15-um all-layer copper, up to 8 metal layers |
| Logic Family | CMOS | — |
| Package Type | 672-ball FC-FBGA (FineLine BGA) | — |
| Package Body Size | 27 x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| 動作温度 | 0 °C to 85 °C (commercial) | 0C to +85C (Commercial) |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Programmable Logic Type | Loadable PLD (in-system programmable) | — |
| Embedded Memory | Embedded System Blocks (ESB) configurable as dual-port RAM/ROM | — |
| PLLs | Up to 4 | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Product Family | — | APEX II |
| Maximum System Gates | — | 1,650,000 |
| Maximum RAM Bits | — | 422,976 |
| User I/O Count | — | 492 |
| パッケージ | — | 672-ball FCBGA (FineLine BGA) |
| Supply Voltage (Core) | — | 1.5 V |
| LVDS Data Rate | — | 1 Gbps per channel (True-LVDS) |
| I/O Standards Supported | — | LVDS, LVPECL, PCML, HyperTransport |
| Speed Grade | — | -7 |
| Configuration Mode | — | Passive Serial, Passive Parallel, JTAG |
| Embedded System Blocks (ESB) | — | Yes - RAM, ROM, CAM, multiplier support |