EP2A25F672C8 vs EP2A25F672I-9 Vergleich
Detaillierter Direktvergleich von EP2A25F672C8 von Altera und EP2A25F672I-9 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A25F672C8 | EP2A25F672I-9 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $951,18 | $195,00 |
| Family | APEX II (EP2A25) | APEX II |
| Logic Elements | 25,000 (typical gates) | — |
| Maximum System Gates | 40,960 | [DATA_NEEDED: maximum system gates] |
| Macrocells / Embedded Logic | 2,432 macros | — |
| User I/O Count | 492 | — |
| Gehäuse | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) | 672-pin FCBGA (FineLine BGA) |
| Propagation Delay (tpd) | 1.69 ns | — |
| Speed Grade | C8 | -9 |
| Betriebstemperatur | 0 C to 85 C (commercial) | — |
| Process Technology | 0.15 microm CMOS, 8-layer copper interconnect | 0.18 µm CMOS |
| I/O Standards Supported | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL | — |
| LVDS Data Rate | 1 Gbps | — |
| PLL Count | 4 | — |
| Embedded Memory | ESB blocks (dual-port RAM, FIFO, CAM, ROM) | — |
| I/O Banks | 16 | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | Non-compliant (legacy product) | [DATA_NEEDED: RoHS status] |
| Logic Elements (typical) | — | 25,000 |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |