EP2A25F672C8 vs EP2A25F672I-9 Comparaison
Comparaison détaillée côte à côte de EP2A25F672C8 par Altera et EP2A25F672I-9 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A25F672C8 | EP2A25F672I-9 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $951,18 | $195,00 |
| Family | APEX II (EP2A25) | APEX II |
| Logic Elements | 25,000 (typical gates) | — |
| Maximum System Gates | 40,960 | [DATA_NEEDED: maximum system gates] |
| Macrocells / Embedded Logic | 2,432 macros | — |
| User I/O Count | 492 | — |
| Boîtier | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) | 672-pin FCBGA (FineLine BGA) |
| Propagation Delay (tpd) | 1.69 ns | — |
| Speed Grade | C8 | -9 |
| Température de fonctionnement | 0 C to 85 C (commercial) | — |
| Process Technology | 0.15 microm CMOS, 8-layer copper interconnect | 0.18 µm CMOS |
| I/O Standards Supported | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL | — |
| LVDS Data Rate | 1 Gbps | — |
| PLL Count | 4 | — |
| Embedded Memory | ESB blocks (dual-port RAM, FIFO, CAM, ROM) | — |
| I/O Banks | 16 | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Statut RoHS | Non-compliant (legacy product) | [DATA_NEEDED: RoHS status] |
| Logic Elements (typical) | — | 25,000 |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |