EP2A25F672C9 vs EP2A25F672I8 Vergleich

Detaillierter Direktvergleich von EP2A25F672C9 von Altera und EP2A25F672I8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672C9 EP2A25F672I8
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $700,00 $125,00
Family APEX II APEX II
Logic Elements (LE) Approximately 25,000 —
Macro Cells 2432 —
User I/O 492 —
Gehäuse 672-ball FCBGA (FineLine BGA) 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch
Package Dimensions 27 mm x 27 mm —
Ball Pitch 1.0 mm —
Process Technology 0.15 µm all-layer copper, up to 8 metal layers 0.15 µm CMOS, up to 8 metal layers
Logic Family CMOS —
Propagation Delay 1.69 ns 1.69 ns (typical)
Betriebstemperatur 0°C to 85°C (Commercial) –40 °C to +85 °C (industrial, 'I' grade)
Versorgungsspannung [DATA_NEEDED: core VCC voltage] —
I/O Standards LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) —
Configuration Passive Serial, Passive Parallel Synchronous, JTAG —
Embedded Memory ESBs for dual-port RAM, ROM, FIFO —
Montageart Surface Mount Surface Mount (BGA)
RoHS-Status [DATA_NEEDED] unknown
Logic Elements / Cells — 24,320
Equivalent Gates — 900,000
Embedded Memory (RAM bits) — 622,592
User I/Os — 492
Number of PLLs — 4
Core Supply Voltage — 1.5 V
Internal Performance — 333 MHz (per legacy datasheet)
LVDS / High-Speed I/O — Yes, up to 1 Gbps
Speed Grade — I8 (industrial, 8-speed-grade per APEX II ordering scheme)
JTAG / Boundary Scan — IEEE 1149.1 compliant
I/O Standards Supported — LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI
Lead-Free Status — unknown

Datenblätter & Ressourcen

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