EP2A40B724C8 vs EP2A40B652C9 Vergleich
Detaillierter Direktvergleich von EP2A40B724C8 von Intel und EP2A40B652C9 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2A40B724C8 - APEX II FPGA 1.5M Gates 540 I/O 724-FCBGA
EP2A40B724C8 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP2A40B724C8 | EP2A40B652C9 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $615,00 | $92,40 |
| Family | APEX II | APEX II |
| Device Logic Elements / Cells | 38400 | — |
| Total System Gates | ~1.5 M | — |
| Total RAM Bits | 655360 | — |
| Number of I/O | 540 | — |
| Number of Logic Gates | [DATA_NEEDED: exact gate count in cells vs system gates] | — |
| Core Supply Voltage | 1.5 V (1.425 V to 1.575 V) | — |
| Maximum Internal Frequency | 376 MHz | — |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.18 µm CMOS |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport (up to 1 Gbps) | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS |
| Gehäuse / Bauform | 724-BBGA, FCBGA (35 x 35 mm) | — |
| Supplier Device Package | 724-BGA | — |
| Betriebstemperatur | 0 °C to 85 °C (TJ) | -40C to +85C (industrial, C9 suffix) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Shipping Media | Tray | — |
| RoHS-Status | [DATA_NEEDED: RoHS status per datasheet] | unknown |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Maximum System Gates | — | 1.5 M (40K logic elements) |
| Logic Elements | — | 40,160 |
| Embedded System Blocks | — | Yes (dual-port RAM, ROM, CAM) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Gehäuse | — | 652-pin BGA |
| Core Voltage | — | 1.5 V |
| Supply Voltage (I/O) | — | 3.3 V (multi-standard I/O supported) |
| Configuration Method | — | SRAM-based, serial/parallel, JTAG IEEE 1149.1 |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| MSL-Level | — | 3 (168 hours floor life) |