EP2A40B724I-9 vs EP2A40B724C9N Vergleich
Detaillierter Direktvergleich von EP2A40B724I-9 von Altera und EP2A40B724C9N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40B724I-9 | EP2A40B724C9N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $605,00 | $99,50 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 (typical) | — |
| Logic Cells | 38400 | — |
| Embedded Memory Bits | 655360 | — |
| Maximum User I/O | 540 (per EP2A40B724 family) | — |
| Gehäuse | 724-ball FCBGA / FineLine BGA | 724-ball FCBGA (Fine-pitch Chip-Scale BGA) |
| Package Code | B724 | — |
| Temperature Grade | Industrial ('I' suffix) | — |
| Betriebs-Sperrschichttemperatur | -40 C to +100 C (industrial) | — |
| Speed Grade | -9 (per APEX II speed bin) | — |
| Peak Reflow Temperature | 220 C | — |
| Core Voltage | 1.5 V (typical APEX II) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL | — |
| Configuration Interface | JTAG, Passive Serial | — |
| PLL | On-chip (per APEX II architecture) | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | — |
| MSL-Level | [DATA_NEEDED: msl level] | — |
| Series | — | EP2A40 |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| System Gates | — | 1,500,000 |
| Logic Elements / Cells | — | 38,400 |
| Maximum Frequency | — | 366 MHz |
| Propagation Delay | — | 2.05 ns |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage | — | 1.5 V |
| User I/O Count | — | 536 |
| Terminal Pitch | — | 1.270 mm |
| Number of Terminals | — | 724 |
| Terminal Form | — | Ball |
| Output Function | — | Macrocells |
| Operating Temperature Grade | — | Industrial (OTHER / per datasheet) |
| Montageart | — | Surface Mount |