EP2A40B724I-9 vs EP2A40B724C9N 对比
详细并排对比 EP2A40B724I-9 出自 Altera 和 EP2A40B724C9N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A40B724I-9 | EP2A40B724C9N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $605.00 | $99.50 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 (typical) | — |
| Logic Cells | 38400 | — |
| Embedded Memory Bits | 655360 | — |
| Maximum User I/O | 540 (per EP2A40B724 family) | — |
| 封装 | 724-ball FCBGA / FineLine BGA | 724-ball FCBGA (Fine-pitch Chip-Scale BGA) |
| Package Code | B724 | — |
| Temperature Grade | Industrial ('I' suffix) | — |
| 工作结温 | -40 C to +100 C (industrial) | — |
| Speed Grade | -9 (per APEX II speed bin) | — |
| Peak Reflow Temperature | 220 C | — |
| Core Voltage | 1.5 V (typical APEX II) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL | — |
| Configuration Interface | JTAG, Passive Serial | — |
| PLL | On-chip (per APEX II architecture) | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | — |
| MSL 等级 | [DATA_NEEDED: msl level] | — |
| Series | — | EP2A40 |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| System Gates | — | 1,500,000 |
| Logic Elements / Cells | — | 38,400 |
| Maximum Frequency | — | 366 MHz |
| Propagation Delay | — | 2.05 ns |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage | — | 1.5 V |
| User I/O Count | — | 536 |
| Terminal Pitch | — | 1.270 mm |
| Number of Terminals | — | 724 |
| Terminal Form | — | Ball |
| Output Function | — | Macrocells |
| Operating Temperature Grade | — | Industrial (OTHER / per datasheet) |
| 安装类型 | — | Surface Mount |